2010. 4. 29 1/3 semiconductor technical data K3520PQ-XH common-drain dual n-channel enhancement mode field effect transistor revision no : 0 general description the K3520PQ-XH is a dual n-channel mosfet designed for use as a bi-directional load switch, facilitated by its common-drain configuration. features ? low on-state resistance r ds(on)1 = 16m ? max (v gs =4.5v, i s =1.0a) r ds(on)2 = 17m ? max (v gs =3.9v, i s =1.0a) r ds(on)3 = 20m ? max (v gs =3.5v, i s =1.0a) maximum rating (ta=25 ? unless otherwise noted) g1 rg rg d s1 g2 d s2 180 10 m + _ 2000 1080 g2 s2 s1 g1 bottom : common drain characteristic symbol rating unit drain-source voltage v dss 24 v gate-source voltage v gss ?? 12 v storage temperature range t stg -55 ?- 150 ? equivalent circuit
2010. 4. 29 2/3 K3520PQ-XH revision no : 0 electrical characteristics (ta=25 ? unless otherwise noted) characteristic symbol test condition min typ max unit drain to source breakdown voltage v (br)dss i d = 250 a, v gs = 0v 24 - - v gate to source breakdown voltage v (br)gss i g = ?? 100 ? , v ds = 0v ?? 12 ?? 14 - v drain cut-off current i dss v ds = 24v, v gs = 0v - - 1.0 ? gate to source leakage current i gss v gs = ?? 12v, v ds = 0v - - ?? 10 ? gate to source threshold voltage v th v ds =v gs, i d =250 a 0.5 1.1 1.5 v drain to source on resistance r ds(on) v gs = 4.5v, i d = 1.0a - 12.5 16.0 m ? v gs = 3.9v, i d = 1.0a - 13.5 17.0 m ? v gs = 3.5v, i d = 1.0a - 15.0 20.0 m ? gate resistance r g f=1mhz - 3.0 - k ? input capacitance c iss v ds = 10v, v gs = 0v, f=1mhz - 600 - pf output capacitance c oss - 115 - reverse transfer capacitance c rss - 83 - total gate charge q g v dd =10v, v gs =3.9v, i s =4.0a - 6.0 - nc gate-source charge q gs - 0.8 - gate-drain charge q gd - 2.5 - source-drain forward voltage v sd v gs = 0v, i s = 1.0a 0.50 0.70 0.86 v
2010. 4. 29 3/3 K3520PQ-XH revision no : 0 2000 1080 g2 s2 s1 g1 bottom : common drain die information contents v alue wafer size 8 inch notch type wafer thickness 180um front metal a -4um back metal ti/ni/ag-1.4um passivation layer yes die size (with scribe lane) 2000 ?? 1080 - 2 scribe lane width 60 - gate pad size 170 ?? 163 - 2 die edge to gate pad 93 - die edge to source pad 70 - gross die(per wafer) 13,470ea
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